View A1020A-1PG256B_4312899.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

v3.0
HiRel FPGAs
Fe a t ur es
* Low-Power 0.8 CMOS Technology
32 0 0D X Fe a t ur es
* Highly Predictable Performance with 100% Automatic Placement and Routing * Device Sizes from 1,200 to 20,000 Gates * Up to 6 Fast, Low-Skew Clock Networks * Up to 202 User-Programmable I/O Pins * * * * * * * * * More Than 500 Macro Functions Up to 1,276 Dedicated Flip-Flops I/O Drive to 10 mA Devices Available to DSCC SMD CQFP and CPGA Packaging Nonvolatile, User Programmable Logic Fully Tested Prior to Shipment 100% Military Temperature Tested (-55C to +125C) QML Certified Devices
* 100 MHz System Logic Integration * Highest Speed FPGA SRAM, up to 2.5 kbits Configurable Dual-Port SRAM * Fast Wide-Decode Circuitry * Low-Power 0.6 CMOS Technology
12 0 0X L Fe at ure s
* Pin for Pin Compatible with ACT 2 * System Performance to 50 MHz over Military Temperature * Low-Power 0.6 CMOS Technology
A CT 2 Fe at ure s
* Proven Reliability Data Available * Successful Military/Avionics Supplier for Over 10 Years
A CT 3 Fe at ure s
* Best-Value, High-Capacity FPGA Family * System Performance to 40 MHz over Military Temperature * Low-Power 1.0 CMOS Technology
A CT 1 Fe at ure s
* Highest-Performance, Highest-Capacity FPGA Family * System Performance to 60 MHz over Military Temperature
* Lowest-Cost FPGA Family * System Performance to 20 MHz over Military Temperature * Low-Power 1.0 CMOS Technology
Pr od uc t F am i l y P r o f i l e (more devices on page 2)
Family Device Capacity System Gates Logic Gates SRAM Bits Logic Modules S-Modules C-Modules Decode Flip-Flops (Maximum) User I/Os (Maximum) Performance System Speed (maximum) Packages (by Pin Count) CPGA CQFP 3200DX A32100DX 15,000 10,000 2,048 1,362 700 662 20 738 152 55 MHz A32200DX 30,000 20,000 2,560 2,414 1,230 1,184 24 1,276 202 55 MHz A1425A 3,750 2,500 NA 310 160 150 NA 435 100 60 MHz 133 132 ACT 3 A1460A 9,000 6,000 NA 848 432 416 NA 976 168 60 MHz 207 196 A14100A 15,000 10,000 NA 1,377 697 680 NA 1,493 228 60 MHz 257 256 1200XL A1280XL 12,000 8,000 1,232 624 608 NA 998 140 50 MHz 176 172
84
208, 256
J an u a r y 2 0 0 0
1
(c) 2000 Actel Corporation
Pr od uc t F am i l y P r o f i l e
Family Device Capacity System Gates Logic Gates SRAM Bits Logic Modules S-Modules C-Modules Decode Flip-Flops (maximum) User I/Os (maximum) Packages (by pin count) CPGA CQFP Performance System Speed (maximum) ACT 2 A1240A 6,000 4,000 NA 684 348 336 NA 568 104 132 -- 40 MHz A1280A 12,000 8,000 NA 1,232 624 608 NA 998 140 176 172 40 MHz ACT 1 A1010B 1,800 1,200 NA 295 -- 295 NA 147 57 84 -- A1020B 3,000 2,000 NA 547 -- 547 NA 273 69 84 84
20 MHz
20 MHz
H i gh - R el i a bi l i t y , L o w - Ri s k So l ut i on
Actel builds the most reliable field programmable gate arrays (FPGAs) in the industry, with overall antifuse reliability ratings of less than 10 Failures-In-Time (FITs), corresponding to a useful life of more than 40 years. Actel FPGAs have been production proven, with more than five million devices shipped and more than one trillion antifuses manufactured. Actel devices are fully tested prior to shipment, with an outgoing defect level of less than 100 ppm. (Further reliability data is available in the Actel Device Reliability Report, at http://www.actel.com/hirel).
B en ef i t s
Mi nim i zed C os t Ri sk
junction temperatures. Actel's non-PLD architecture delivers lower dynamic operating current. Our reliability tests show a very low failure rate of 6.6 FITs at 90C junction temperature with no degradation in AC performance. Special stress testing at wafer test eliminates infant mortalities prior to packaging.
M ini m ized S ecu ri ty R is k
Reverse engineering of programmed Actel devices from optical or electrical data is extremely difficult. Programmed antifuses cannot be identified from a photograph or by using an SEM. The antifuse map cannot be deciphered either electrically or by microprobing. Each device has a silicon signature that identifies its origins, down to the wafer lot and fabrication facility.
M ini m ized T es ti ng Ri sk
With Actel's line of development tools, designers can produce as many chips as they choose for just the cost of the device itself. There will be no NRE charges to cut into the development budget each time a new design is tried.
M i n im i z e d T i m e R is k
After the design is entered, placement and routing is automatic, and programming the device takes only about 5 to 15 minutes for an average design. Designers save time in the design entry process by using tools with which they are familiar.
Mi nim i zed R el iabi li ty R is k
Unprogrammed Actel parts are extensively tested at the factory. Routing tracks, logic modules, and programming, debug and test circuits are 100 percent tested before shipment. AC performance is ensured by special speed path tests, and programming circuitry is verified on test antifuses. During the programming process, an algorithm is run to ensure that all antifuses are correctly programmed. In addition, Actel's Silicon Explorer diagnostic tool uses ActionProbe circuitry, allowing 100 percent observability of all internal nodes to check and debug the design.
A c t e l FP G A De sc r i p t i o n
The PLICE antifuse is a one-time programmable, nonvolatile connection. Since Actel devices are permanently programmed, no downloading from EPROM or SRAM storage is required. Inadvertent erasure is impossible, and there is no need to reload the program after power disruptions. Fabrication using a low-power CMOS process means cooler
The Actel families of FPGAs offer a variety of packages, speed/performance characteristics, and processing levels for use in all high reliability and military applications. Devices are implemented in a silicon gate, two-level metal CMOS process, utilizing Actel's PLICE antifuse technology. This
2
H iR e l F PG A s
unique architecture offers gate array flexibility, high performance, and quick turnaround through user programming. Device utilization is typically 95 percent of available logic modules. All Actel devices include on-chip clock drivers and a hard-wired distribution network. User-definable I/Os are capable of driving at both TTL and CMOS drive levels. Available packages for the military are the Ceramic Quad Flat Pack (CQFP) and the Ceramic Pin Grid Array (CPGA). See the "Product Plan" section on page 6 for details.
Q M L C e r t i f i c at i on
A CT 3 De sc r i p t i o n
The ACT 3 family is the third-generation Actel FPGA family. This family offers the highest-performance and highest-capacity devices, ranging from 2,500 to 10,000 gates, with system performance up to 60 MHz over the military temperature range. The devices have four clock distribution networks, including dedicated array and I/O clocks. In addition, the ACT 3 family offers the highest I/O-to-gate ratio available. ACT 3 devices are manufactured using 0.8 CMOS technology.
12 0 0X L / 32 00 D X D e sc r i p t i o n
Actel has achieved full QML certification, demonstrating that quality management, procedures, processes, and controls are in place and comply with MIL-PRF-38535, the performance specification used by the Department of Defense for monolithic integrated circuits. QML certification is a good example of Actel's commitment to supplying the highest quality products for all types of high-reliability, military and space applications. Many suppliers of microelectronics components have implemented QML as their primary worldwide business system. Appropriate use of this system not only helps in the implementation of advanced technologies, but also allows for a quality, reliable and cost-effective logistics support throughout QML products' life cycles.
D ev el o pm en t T oo l S up po r t
3200DX and 1200XL FPGAs were designed to integrate system logic which is typically implemented in multiple CPLDs, PALs, and FPGAs. These devices provide the features and performance required for today's complex, high-speed digital logic systems. The 3200DX family offers the industry's fastest dual-port SRAM for implementing fast FIFOs, LIFOs, and temporary data storage.
A CT 2 De sc r i p t i o n
The ACT 2 family is the second-generation Actel FPGA family. This family offers the best-value, high-capacity devices, ranging from 4,000 to 8,000 gates, with system performance up to 40 MHz over the military temperature range. The devices have two routed array clock distribution networks. ACT 2 devices are manufactured using 1.0 CMOS technology.
A CT 1 De sc r i p t i o n
The HiRel devices are fully supported by Actel's line of FPGA development tools, including the Actel DeskTOP series and Designer Advantage tools. The Actel DeskTOP Series is an integrated design environment for PCs that includes design entry, simulation, synthesis, and place and route tools. Designer Advantage is Actel's suite of FPGA development point tools for PCs and Workstations that includes the ACTgen Macro Builder, Designer with DirectTime timing driven place and route and analysis tools, and device programming software. In addition, the HiRel devices contain ActionProbe circuitry that provides built-in access to every node in a design, enabling 100 percent real-time observation and analysis of a device's internal logic nodes without design iteration. The probe circuitry is accessed by Silicon Explorer, an easy to use integrated verification and logic analysis tool that can sample data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer attaches to a PC's standard COM port, turning the PC into a fully functional 18 channel logic analyzer. Silicon Explorer allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds.
The ACT 1 family is the first Actel FPGA family and the first antifuse-based FPGA. This family offers the lowest-cost logic integration, with devices ranging from 1,200 to 2,000 gates, with system performance up to 20 MHz over the military temperature range. The devices have one routed array clock distribution network. ACT 1 devices are manufactured using 1.0 CMOS technology.
3
M i l i t a r y D e v i c e Or de r i n g I n f o r m a t i on
A14100
A
-
1
CQ
256
B
Application (Temperature Range) C = Commercial (0 to +70C) M = Military (-55 to +125C) B = MIL-STD-883 Class B E = Extended Flow (Space Level) Package Lead Count Package Type CQ = Ceramic Quad Flat Pack (CQFP) PG = Ceramic Pin Grid Array (CPGA) Speed Grade Std = Standard Speed -1 = Approximately 15% faster than Standard Device Revision Part Number A1010 = A1020 = A1240 = A1280 = A1425 = A1460 = A14100 = A32100 = A32200 =
1,200 Gates--ACT 1 2,000 Gates--ACT 1 4,000 Gates--ACT 2 8,000 Gates--ACT 2/1200XL 2,500 Gates--ACT 3 6,000 Gates--ACT 3 10,000 Gates--ACT 3 10,000 Gates--3200DX 20,000 Gates--3200DX
4
H iR e l F PG A s
D ES C SM D / A ct el P ar t N um b e r C r os s R e f e r en ce
Actel Part Number (Gold Leads) A1010B-PG84B A1010B-1PG84B A1020B-PG84B A1020B-1PG84B A1020B-CQ84B A1020B-1CQ84B A1240A-PG132B A1240A-1PG132B A1280A-PG176B A1280A-1PG176B A1280A-CQ172B A1280A-1CQ172B A1425A-PG133B A1425A-1PG133B A1425A-CQ132B A1425A-1CQ132B A1460A-PG207B A1460A-1PG207B A1460A-CQ196B A1460A-1CQ196B A14100A-PG257B A14100A-1PG257B A14100A-CQ256B A14100A-1CQ256B A32100DX-CQ84B A32100DX-1CQ84B A32200DX-CQ256B A32200DX-1CQ256B A32200DX-CQ208B A32200DX-1CQ208B DSCC SMD (Gold Leads) 5962-9096403MXC 5962-9096404MXC 5962-9096503MUC 5962-9096504MUC 5962-9096503MTC 5962-9096504MTC 5962-9322101MXC 5962-9322102MXC 5962-9215601MXC 5962-9215602MXC 5962-9215601MYC 5962-9215602MYC 5962-9552001MXC 5962-9552002MXC 5962-9552001MYC 5962-9552002MYC 5962-9550801MXC 5962-9550802MXC 5962-9550801MYC 5962-9550802MYC 5962-9552101MXC 5962-9552102MXC 5962-9552101MYC 5962-9552102MYC 5962-9875901QXC 5962-9857902QXC 5962-9952701QXC 5962-9952702QXC 5962-9952701QYC 5962-9952702QYC DSCC SMD (Solder Dipped) 5962-9096403MXA 5962-9096404MXA 5962-9096503MUA 5962-9096504MUA 5962-9096503MTA 5962-9096504MTA 5962-9322101MXA 5962-9322102MXA 5962-9215601MXA 5962-9215602MXA 5962-9215601MYA 5962-9215602MYA N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
5
Pr od uc t P l a n
Speed Grade Application C M B E
3 2 00 D X F a m i l y
A32100DX Device 84-pin Ceramic Quad Flat Pack (CQFP) A32200DX Device 208-pin Ceramic Quad Flat Pack (CQFP) 256-pin Ceramic Quad Flat Pack (CQFP)
Std
-1*
--
-- --
A C T 3 F am i l y
A1425A Device 132-pin Ceramic Quad Flat Pack (CQFP) 133-pin Ceramic Pin Grid Array (CPGA) A1460A Device 196-pin Ceramic Quad Flat Pack (CQFP) 207-pin Ceramic Pin Grid Array (CPGA) A14100A Device 256-pin Ceramic Quad Flat Pack (CQFP) 257-pin Ceramic Pin Grid Array (CPGA)
1 2 00 X L F am i l y
A1280XL Device 172-pin Ceramic Quad Flat Pack (CQFP) 176-pin Ceramic Pin Grid Array (CPGA) -- --
A C T 2 F am i l y
A1240A Device 132-pin Ceramic Pin Grid Array (CPGA) A1280A Device 172-pin Ceramic Quad Flat Pack (CQFP) 176-pin Ceramic Pin Grid Array (CPGA) --
A C T 1 F am i l y
A1010B Device 84-pin Ceramic Pin Grid Array (CPGA) A1020B Device 84-pin Ceramic Quad Flat Pack (CQFP) 84-pin Ceramic Pin Grid Array (CPGA) Applications: C M B E = = = = Commercial Military MIL-STD-883 Extended Flow Availability: = Available -- = Not Planned *Speed Grade: -1 = Approx. 15% faster than Standard --
6
H iR e l F PG A s
32 0 0D X De v i ce R es ou r c es
User I/Os FPGA Device Type A32100DX A32200DX Logic Modules 1,362 2,414 Gate Array Equivalent Gates 10,000 20,000 CQFP 84-pin 60 -- 208-pin -- 176 256-pin -- 202
A CT 3 De vi c e Re s ou r c es
User I/Os FPGA Device Type A1425A A1460A A14100A Logic Modules 310 848 1,377 Gate Array Equivalent Gates 2,500 6,000 10,000 CQFP 132-pin 100 -- -- 196-pin -- 168 -- 256-pin -- -- 228 133-pin 100 -- -- CPGA 207-pin -- 168 -- 257-pin -- -- 228
12 0 0X L De vi c e Re so u r ce s
User I/Os FPGA Device Type A1280XL Logic Modules 1,232 Gate Array Equivalent Gates 8,000 CQFP 172-pin 140 CPGA 176-pin 140
A CT 2 De vi c e Re s ou r c es
User I/Os FPGA Device Type A1240A A1280A Logic Modules 684 1,232 Gate Array Equivalent Gates 4,000 8,000 CQFP 172-pin -- 140 132-pin 104 -- CPGA 176-pin -- 140
A CT 1 De vi c e Re s ou r c es
User I/Os FPGA Device Type A1010B A1020B Logic Modules 295 547 Gate Array Equivalent Gates 1,200 2,000 CQFP 84-pin -- 69 CPGA 84-pin 57 69
7
A ct e l M I L - ST D - 88 3 Pr od uc t F l ow
Step 1. 2. 3. 4. Screen Internal Visual Temperature Cycling Constant Acceleration Seal a. Fine b. Gross Visual Inspection Pre-Burn-In Electrical Parameters Burn-in Test Interim (Post-Burn-In) Electrical Parameters Percent Defective Allowable Final Electrical Test a. Static Tests (1) 25C (Subgroup 1, Table I) (2) -55C and +125C (Subgroups 2, 3, Table I) b. Functional Tests (1) 25C (Subgroup 7, Table I) (2) -55C and +125C (Subgroups 8A and 8B, Table I) c. Switching Tests at 25C (Subgroup 9, Table I) 11. Note: External Visual 883 Method 2010, Test Condition B 1010, Test Condition C 2001, Test Condition D or E, Y1, Orientation Only 1014 100% 100% 2009 In accordance with applicable Actel device specification 1015, Condition D, 160 hours @ 125C or 80 hours @ 150C In accordance with applicable Actel device specification 5% In accordance with applicable Actel device specification, which includes a, b, and c: 100% 5005 5005 100% 5005 5005 100% 5005 2009 100% 100% 100% 100% 100% All Lots 883--Class B Requirement 100% 100% 100%
5. 6. 7. 8. 9. 10.
When Destructive Physical Analysis (DPA) is performed on Class B devices, the step coverage requirement as specified in Method 2018 must be waived.
8
H iR e l F PG A s
A ct e l E xt e n de d F l o w 1
Step 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Screen Wafer Lot Acceptance2 Destructive In-Line Bond Pull Internal Visual Serialization Temperature Cycling Constant Acceleration Particle Impact Noise Detection Radiographic Pre-Burn-In Test Burn-in Test Interim (Post-Burn-In) Electrical Parameters Reverse Bias Burn-In Interim (Post-Burn-In) Electrical Parameters Percent Defective Allowable (PDA) Calculation Final Electrical Test a. Static Tests (1) 25C (Subgroup 1, Table1) (2) -55C and +125C (Subgroups 2, 3, Table 1) b. Functional Tests (1) 25C (Subgroup 7, Table 15) (2) -55C and +125C (Subgroups 8A and B, Table 1) c. Switching Tests at 25C (Subgroup 9, Table 1) 16. Seal a. Fine b. Gross 17. External Visual 2009 100% 1010, Condition C 2001, Condition D or E, Y1 Orientation Only 2020, Condition A 2012 (one view only) In accordance with applicable Actel device specification 1015, Condition D, 240 hours @ 125C minimum In accordance with applicable Actel device specification 1015, Condition C, 72 hours @ 150C minimum In accordance with applicable Actel device specification 5%, 3% Functional Parameters @ 25C In accordance with Actel applicable device specification which includes a, b, and c: 5005 5005 100% 5005 5005 100% 5005 1014 100%
3
Method 5007 with Step Coverage Waiver 2011, Condition D 2010, Condition A
Requirement All Lots Sample 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% 100% All Lots 100% 100%
Notes: 1. Actel offers the extended flow for customers who require additional screening beyond the requirements of the MIL-STD-833, Class B. Actel is compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this extended flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. The exceptions to Method 5004 are shown in notes 2 and 3 below. 2. Wafer lot acceptance is performed to Method 5007; however, the step coverage requirement as specified in Method 2018 must be waived. 3. MIL-STD-883, Method 5004 requires 100 percent Radiation latch-up testing (Method 1020). Actel will not be performing any radiation testing, and this requirement must be waived in its entirety.
9
A bs ol u t e M ax i m u m Ra t i n gs 1
Free air temperature range Symbol VCC VI VO IIO TSTG Parameter DC Supply Voltage2, 3, 4 Input Voltage Output Voltage I/O Source Sink Current5 Storage Temperature Limits -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 -65 to +150 Units V V V mA C
R ec o m m en d ed O pe r a t i ng C on d i t i o ns
Parameter Temperature Range1 Power Supply Tolerance2 Commercial 0 to +70 5 Military -55 to +125 10 Units C %VCC
Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommended operating conditions. 2. VPP = VCC , except during device programming. 3. VSV = VCC , except during device programming. 4. VKS = GND , except during device programming. 5. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5V or less than GND - 0.5V, the internal protection diode will be forward biased and can draw excessive current.
Notes: 1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. 2. All power supplies must be in the recommended operating range. For more information, refer to the Power-Up Design Considerations application note at http://www.actel.com/appnotes.
El e c t r i c al S p ec i f i c at i o n s
Commercial Symbol VOH1, 2 VOL1, 2 VIH VIL IIN IOZ CIO ICC(S) Parameter HIGH Level Output Test Condition IOH = -4 mA (CMOS) IOH = -6 mA (CMOS) LOW Level Output HIGH Level Input LOW Level Input Input Leakage 3-state Output Leakage I/O Capacitance3, 4 Standby VCC Supply Current VI = VCC or GND, IO = 0 mA ACT 1 ACT 2/3/1200XL/3200DX ICC(D) Dynamic VCC Supply Current 3 2 20 20 mA mA IOL = +6 mA (CMOS) TTL Inputs TTL Inputs VI = VCC or GND VO = VCC or GND 2.0 -0.3 -10 -10 3.84 0.33 VCC + 0.3 0.8 +10 +10 10 2.0 -0.3 -10 -10 0.4 VCC + 0.3 0.8 +10 +10 10 Min. Max. Min. 3.7 Military Max. Units V V V V V A A pF
See the "Power Dissipation" section on page 11.
Notes: 1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required. 2. Tested one output at a time, VCC = min. 3. Not tested; for information only. 4. VOUT = 0V, f = 1 MHz
10
H iR e l F PG A s
Pa c ka ge T he r m a l C ha r a ct e r i s t i c s
The device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates.
Maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for a CPGA 176-pin package at military temperature is as follows:
Max. junction temp. (C) - Max. military temp. = 150C - 125C = 1.1 W ---------------------------------------------------------------------------------------------------------------------------------------------------23C/W ja (C/W) ja Still Air 33 25 25 23 21 15 40 35 25 23 20 ja 300 ft/min 20 16 15 12 10 8 30 25 20 15 10
Package Type Ceramic Pin Grid Array
Pin Count 84 132 133 176 207 257 84 132 172 196 256
jc 6.0 4.8 4.8 4.6 3.5 2.8 7.8 7.2 6.8 6.4 6.2
Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W
Ceramic Quad Flat Pack
Po w e r D i s s i pa t i o n
Gener al P ow er E quat i on
P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N + IOH * (VCC - VOH) * M where: ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. Accurate values for N and M are difficult to determine because they depend on the family type, on the design, and on the system I/O. The power can be divided into two components--static and active.
S tat i c P ow er Co m ponen t
The power due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial, worst-case conditions. Family ACT 3 1200XL/3200DX ACT 2 ACT 1 ICC 2 mA 2 mA 2 mA 3 mA VCC 5.25V 5.25V 5.25V 5.25V Power 10.5 mW 10.5 mW 10.5 mW 15.8 mW
The static power dissipated by TTL loads depends on the number of outputs driving high or low and the DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33V will generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high.
Ac ti ve P ower Com po nent
Actel FPGAs have small static power components that result in power dissipation lower than that of PALs or PLDs. By integrating multiple PALs or PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved.
Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totempole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that
11
can be combined with frequency and voltage to represent active power dissipation.
E quiv al ent C apac it ance
where: m n p q1 q2 = Number of logic modules switching at fm = Number of input buffers switching at fn = Number of output buffers switching at fp = Number of clock loads on the first routed array clock (all families) = Number of clock loads on the second routed array clock (ACT 2, 1200XL, 3200DX, ACT 3 only) = Fixed capacitance due to first routed array clock (all families) = Fixed capacitance due to second routed array clock (ACT 2, 1200XL, 3200DX, ACT 3 only) = Fixed number of clock loads on the dedicated array clock (ACT 3 only) = Fixed number of clock loads on the dedicated I/O clock (ACT 3 only) = Equivalent capacitance of logic modules in pF = Equivalent capacitance of input buffers in pF = Equivalent capacitance of output buffers in pF = Equivalent capacitance of routed array clock in pF = Equivalent capacitance of dedicated array clock in pF = Equivalent capacitance of dedicated I/O clock in pF = Output lead capacitance in pF = Average logic module switching rate in MHz = Average input buffer switching rate in MHz = Average output buffer switching rate in MHz = Average first routed array clock rate in MHz (all families) = Average second routed array clock rate in MHz (ACT 2, 1200XL, 3200DX, ACT 3 only) = Average dedicated array clock rate in MHz (ACT 3 only) = Average dedicated I/O clock rate in MHz (ACT 3 only)
The power dissipated by a CMOS circuit can be expressed by Equation 1: Power (uW) = CEQ * VCC2 * F where: CEQ VCC F = Equivalent capacitance in pF = Power supply in volts (V) = Switching frequency in MHz (1)
r1 r2 s1 s2 CEQM CEQI CEQO CEQCR CEQCD
Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit component of interest. Measurements are made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency independent so that the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown below.
CE Q Val ues f or Act el FP G A s
1200XL ACT 3 3200DX ACT 2 ACT 1 Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR) Dedicated Clock Buffer Loads (CEQCD) I/O Clock Buffer Loads (CEQCI) 6.7 7.2 10.4 1.6 0.7 0.9 5.2 11.6 23.8 3.5 N/A N/A 5.8 12.9 23.8 3.9 N/A N/A 3.7 22.1 31.2 4.6
CEQCI N/A CL N/A fm fn fp fq1 fq2 fs1 fs2
To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piecewise linear summation over all components that applies to all ACT 1, 1200XL, 3200DX, ACT 2, and ACT 3 devices. Since the ACT 1 family has only one routed array clock, the terms labeled routed_Clk2, dedicated_Clk, and IO_Clk do not apply. Similarly, the ACT 2 family has two routed array clocks, and the dedicated_Clk and IO_Clk terms do not apply. For ACT 3 devices, all terms will apply. Power = VCC2 * [(m * CEQM* fm)modules + (n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk + (s2 * CEQCI * fs2)IO_Clk] (2)
12
H iR e l F PG A s
Fix ed Capa cit anc e V alu es for Act el FP GA s (pF)
Fix ed Clo ck Loads ( s 1 / s 2 -- A CT 3 O nl y )
Device Type A1010B A1020B A1240A A1280A A1280XL A1425A A1460A A14100A A32100DX A32200DX
Type Logic modules (m) Input switching (n) Outputs switching (p)
r1 routed_Clk1 41 69 134 168 168 75 165 195 178 230
r2 routed_Clk2 n/a n/a 134 168 168 75 165 195 178 230
ACT 3 80% of modules # inputs/4 #outputs/4 40% of sequential modules 40% of sequential modules 35 pF F/10 F/5 F/10 F/2 F/2 F F
Device Type A1425A A1460A A14100A
s1 Clock Loads on Dedicated Array Clock 160 432 697
s2 Clock Loads on Dedicated I/O Clock 100 168 228
De ter m in ing Av er age S wi tc hing Fr equ ency
To determine the switching frequency for a design, you must have a detailed understanding of the data values input to the circuit. The guidelines in the table below are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation.
3200DX/ACT 2/1200XL 80% of modules # inputs/4 #outputs/4 40% of sequential modules 40% of sequential modules 35 pF F/10 F/5 F/10 F F/2 n/a n/a
ACT 1 90% of modules # inputs/4 #outputs/4 40% of modules n/a 35 pF F/10 F/5 F/10 F n/a n/a n/a
First routed array clock loads (q1) Second routed array clock loads (q2) Load capacitance (CL) Average logic module switching rate (fm) Average input switching rate (fn) Average output switching rate (fp) Average first routed array clock rate (fq1) Average second routed array clock rate (fq2) Average dedicated array clock rate (f s1) Average dedicated I/O clock rate (fs2)
13
32 0 0D X Ti m i ng M od el ( Lo g i c F un c t i on s us i ng A r r a y C l o ck s) *
Input Delays I/O Module tINPY = 1.9 ns t IRD1 = 2.2 ns
Internal Delays
Predicted Routing Delays
Output Delays I/O Module
Combinatorial Module D Q tPD = 3.1 ns tRD1 = 1.3 ns tRD2 = 1.9 ns tRD4 = 3.3 ns
tDLH = 6.3 ns
G tINH = 0.0 ns tINSU = 0.7 ns tINGO = 4.0 ns Decode Module tPDD = 3.3 ns I/O Module tDLH = 6.3 ns
tRDD = 0.5 ns
Sequential Logic Module
Combinatorial Logic included in tSUD
D
Q
tRD1 = 1.3 ns
D
Q tENHZ = 11.5 ns
G tLH = 0.0 ns tLSU = 0.4 ns tGHL= 12.4 ns
tSU = 0.5 ns tHD = 0.0 ns ARRAY CLOCKS tCKH = 6.5 ns FMAX = 140 MHz
tCO = 3.1 ns
*Values shown for A32100DX-1 at worst-case military conditions.
14
H iR e l F PG A s
32 0 0D X Ti m i ng M od el ( Lo g i c F un c t i on s us i ng Q ua dr an t C l o ck s) *
Input Delays I/O Module tINPY = 1.9 ns t IRD1 = 2.2 ns
Internal Delays
Predicted Routing Delays
Output Delays I/O Module
Combinatorial Module D Q tPD = 3.1 ns tRD1 = 1.3 ns tRD2 = 1.9 ns tRD4 = 3.3 ns
tDLH = 6.3 ns
G tINH = 0.0 ns tINSU = 0.7 ns tINGO = 4.0 ns Decode Module tPDD = 3.3 ns I/O Module tDLH = 6.3 ns
tRDD = 0.5 ns
Sequential Logic Module
Combinatorial Logic included in tSUD
D
Q
tRD1 = 1.3 ns
D
Q tENHZ = 11.5 ns
G tLH = 0.0 ns tLSU = 0.4 ns tGHL= 12.4 ns
tSU = 0.5 ns tHD = 0.0 ns QUADRANT CLOCKS tCKH = 12 ns**
tCO = 3.1 ns
FMAX = 100 MHz
* Values shown for A32100DX-1 at worst-case military conditions. ** Load dependent.
15
32 0 0D X Ti m i ng M od el ( SR A M Fu n ct i on s) *
Input Delays I/O Module tINPY = 1.9 ns t IRD1 = 2.2 ns
D
Q
G tINSU = 0.7 ns tINH = 0.0 ns tINGO = 4.0 ns
Predicted Routing Delays WD [7:0] WRAD [5:0] BLKEN WEN WCLK tADSU = 2.1 ns tADH = 0.0 ns tWENSU = 3.5 ns tBENS = 3.6 ns RD [7:0] RDAD [5:0] REN tRD1 = 1.3 ns
I/O Module tDLH = 6.3 ns
D
Q
RCLK tADSU = 2.1 ns tADH = 0.0 ns tRENSU = 0.8 ns tRCO = 4.4 ns
G tGHL = 12.4 ns tLSU = 0.4 ns tLH = 0.0 ns
ARRAY CLOCKS FMAX = 140 MHz
*Values shown for A32100DX-1 at worst-case military conditions.
16
H iR e l F PG A s
12 0 0X L Ti m i n g M od el *
Input Delays
Internal Delays
Combinatorial I/O Module Logic Module tINYL = 1.7 ns t IRD2 = 5.2 ns
Predicted Routing Delays
Output Delays I/O Module
tDLH = 6.6 ns D Q tPD = 3.7 ns tRD1 = 1.7 ns tRD2 = 2.5 ns tRD4 = 3.7 ns tRD8 = 7.0 ns
G tINH = 0.0 ns tINSU = 0.4 ns tINGL = 3.7 ns Sequential Logic Module
Combinatorial Logic included in tSUD
I/O Module tDLH = 6.6 ns
D
Q tRD1 = 1.7 ns
D
Q tENHZ = 7.5 ns
G tOUTH = 0.0 ns tOUTSU = 0.4 ns tGLH = 5.9 ns
ARRAY CLOCKS
tCKH = 7.1 ns FMAX = 110 MHz
FO = 256
tSU = 0.4 ns tHD = 0.0 ns
tCO = 3.7 ns
tLCO = 10.7 ns (64 loads, pad-pad)
*Values shown for A1280XL-1 at worst-case military conditions. Input module predicted routing delay.
17
Pa r a m et er M ea su r e m en t
O ut put B uf f er D el ays
E D TRIBUFF PAD To AC test loads (shown below)
VCC In PAD VOL tDLH 50% 50% VOH 1.5V tDHL GND 1.5V E PAD
VCC 50% VCC 50% 1.5V VOL tENZL tENLZ GND 10% E PAD GND
VCC 50% 50% VOH 1.5V tENZH tENHZ GND 90%
AC Test Load
Load 1 (Used to measure propagation delay)
Load 2 (Used to measure rising/falling edges) VCC GND
To the output under test
50 pF To the output under test
R to VCC for tPLZ/tPZL R to GND for tPHZ/tPZH R = 1 k 50 pF
Inpu t Buffe r De lay s
Com b ina tor i al Macr o Del ay s
PAD
INBUF
Y VCC S, A, or B
S A B
Y
3V PAD Y GND tINYH 1.5V 1.5V VCC 50% tINYL 0V 50% Y GND Y
50% 50% VCC 50% tPLH 50% tPHL
GND 50% tPHL VCC GND tPLH 50%
18
H iR e l F PG A s
Se q ue nt i al T i m i n g C h ar ac t er i st i c s
Fl ip- Fl ops and La tch es (AC T 3)
D E CLK
Y CLR
(Positive edge triggered)
tHD D
1
tSUD G, CLK
tWCLKA tSUENA tHENA
tA
E tCO Q tCLR CLR tWASYN Note: 1. D represents all data functions involving A, B, and S for multiplexed flip-flops.
19
Se q ue nt i al T i m i n g C h ar ac t er i st i c s (continued)
Fl ip- Fl ops and La tch es (120 0XL /3 200D X, AC T 2, a nd A CT 1)
D E CLK
PRE CLR
Y
(Positive edge triggered)
tHD D
1
tSUD G, CLK
tWCLKA tSUENA tHENA
tA
E tCO Q tRS PRE, CLR tWASYN
Note: 1. D represents all data functions involving A, B, and S for multiplexed flip-flops.
20
H iR e l F PG A s
Se q ue nt i al T i m i n g C h ar ac t er i st i c s (continued)
Inp ut Bu ffer La tc hes (A CT 2 and 120 0XL /3 200D X)
PAD G
IBDL
CLK
PAD CLKBUF
PAD tINH G tINSU tHEXT CLK tSUEXT
Out put Buffe r Lat che s (AC T 2 and 1200 XL/ 320 0DX )
D OBDLHS G
PAD
D tOUTSU G tOUTH
21
D ec od e Mo d ul e T i m i ng
A B C D E F G
Y H
VCC A-G, H 50% VCC Y tPHL tPLH
SR A M T i m i ng C ha r a ct er i s t i c s
Write Port WRAD [5:0] BLKEN WEN WCLK WD [7:0] RAM Array 32x8 or 64x4 (256 bits)
Read Port RDAD [5:0] LEW REN RCLK RD [7:0]
22
H iR e l F PG A s
D ua l - Po r t SR A M Ti m i n g W av ef or m s
3200 DX S RA M W ri te Ope rat i on
tRCKHL WCLK tADSU WD[7:0] WRAD[5:0] Valid tWENSU WEN tBENSU BLKEN Valid tBENH tWENH tADH
tRCKHL
Note:
Identical timing for falling-edge clock.
3200 DX S RA M S y nch ro nous R ead Oper at io n
tCKHL RCLK
tRCKHL
tRENSU REN tADSU RDAD[5:0] Valid
tRENH
tADH
tRCO tDOH RD[7:0] Old Data New Data
Note:
Identical timing for falling-edge clock.
23
3200 DX S RA M A sy nc hronous R ead Oper at i on-- Ty pe 1
(Read Address Controlled)
tRDADV RDAD[5:0] ADDR1 tDOH RD[7:0] Data 1 ADDR2 tRPD Data 2
3200 DX S RA M A sy nc hronous R ead Oper at i on-- Ty pe 2
(Write Address Controlled)
WEN
tWENSU
tWENH
WD[7:0] WRAD[5:0] BLKEN
Valid tADSU tADH tRPD tDOH
WCLK
RD[7:0]
Old Data
New Data
24
H iR e l F PG A s
A CT 1 Ti m i n g Ch a r ac t e r i s t i cs
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Logic Module Propagation Delays tPD1 tPD2 tCO tGO tRS Single Module Dual Module Macros Sequential Clk to Q Latch G to Q Flip-Flop (Latch) Reset to Q 4.7 10.8 4.7 4.7 4.7 5.5 12.7 5.5 5.5 5.5 ns ns ns ns ns
Logic Module Predicted Routing Delays1 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
2
1.5 2.3 3.4 5.0 10.6
1.7 2.7 4.0 5.9 12.5
ns ns ns ns ns
Logic Module Sequential Timing tSUD tHD tSUENA tHENA tWCLKA tWASYN tA fMAX
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency
8.8 0.0 8.8 0.0 10.9 10.9 23.2 44
10.4 0.0 10.4 0.0 12.9 12.9 27.3 37
ns ns ns ns ns ns ns MHz
Input Module Propagation Delays tINYH tINYL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Pad to Y High Pad to Y Low
1, 3
4.9 4.9
5.8 5.8
ns ns
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1.5 2.3 3.4 5.0 10.6
1.7 2.7 4.0 5.9 12.5
ns ns ns ns ns
Notes: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2. Setup times assume fanout of 3. Further derating information can be obtained from the DirectTime Analyzer utility. 3. Optimization techniques may further reduce delays by 0 to 4 ns.
25
A CT 1 Ti m i n g Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 21.7 23.2 46 44 10.4 10.9 10.4 10.9 1.9 2.9 25.6 27.3 40 37 7.8 8.9 10.3 11.2 12.2 12.9 12.2 12.9 2.2 3.4 9.2 10.5 12.1 13.2 ns ns ns ns ns ns MHz
TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z Delta Low to High Delta High to Low 12.1 13.8 12.0 14.6 16.0 14.5 0.09 0.12 14.2 16.3 14.1 17.1 18.8 17.0 0.11 0.15 ns ns ns ns ns ns ns/pF ns/pF
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z Delta Low to High Delta High to Low 15.1 11.5 12.0 14.6 16.0 14.5 0.16 0.09 17.7 13.6 14.1 17.1 18.8 17.0 0.18 0.11 ns ns ns ns ns ns ns/pF ns/pF
Notes: 1. Delays based on 50 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.
26
H iR e l F PG A s
A 12 40 A Ti m i ng Ch a r ac t e r i s t i cs
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description
1
`Std' Speed Min. Max. Units
Min.
Max.
Logic Module Propagation Delays tPD1 tCO tGO tRS tRD1 tRD2 tRD3 tRD4 tRD8 Single Module
5.2 5.2 5.2 5.2
2
6.1 6.1 6.1 6.1
ns ns ns ns
Sequential Clk to Q Latch G to Q Flip-Flop (Latch) Reset to Q
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
3, 4
1.9 2.4 3.1 4.3 6.6
2.2 2.8 3.7 5.0 7.7
ns ns ns ns ns
Logic Module Sequential Timing tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency
0.5 0.0 1.3 0.0 7.4 7.4 14.8 2.5 -3.5 0.0 0.5 63
0.5 0.0 1.3 0.0 8.1 8.1 18.6 2.5 -3.5 0.0 0.5 54
ns ns ns ns ns ns ns ns ns ns ns MHz
Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
27
A 12 40 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Input Module Propagation Delays tINYH tINYL tINGH tINGL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Pad to Y High Pad to Y Low G to Y High G to Y Low
1
4.0 3.6 6.9 6.6
4.7 4.3 8.1 7.7
ns ns ns ns
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
5.8 6.7 7.5 8.2 10.9
6.9 7.8 8.8 9.7 12.9
ns ns ns ns ns
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 0.0 0.0 8.6 13.8 11.5 12.2 87 82 5.7 6.0 5.7 6.0 0.6 3.1 0.0 0.0 8.6 13.8 13.5 14.3 74 70 13.3 16.3 13.3 16.5 6.7 7.1 6.7 7.1 0.6 3.1 15.7 19.2 15.7 19.5 ns ns ns ns ns ns ns ns MHz
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0 to 4 ns.
28
H iR e l F PG A s
A 12 40 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low Delta Low to High Delta High to Low 11.0 13.9 12.3 16.1 9.8 11.5 12.4 15.5 0.09 0.17 13.0 16.4 14.4 19.0 11.5 13.6 14.6 18.2 0.11 0.20 ns ns ns ns ns ns ns ns ns/pF ns/pF
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low Delta Low to High Delta High to Low 14.0 11.7 12.3 16.1 9.8 11.5 12.4 15.5 0.17 0.12 16.5 13.7 14.4 19.0 11.5 13.6 14.6 18.2 0.20 0.15 ns ns ns ns ns ns ns ns ns/pF ns/pF
Notes: 1. Delays based on 50 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.
29
A 12 80 A Ti m i ng Ch a r ac t e r i s t i cs
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description
1
`Std' Speed Min. Max. Units
Min.
Max.
Logic Module Propagation Delays tPD1 tCO tGO tRS tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Single Module
5.2 5.2 5.2 5.2
2
6.1 6.1 6.1 6.1
ns ns ns ns
Sequential Clk to Q Latch G to Q Flip-Flop (Latch) Reset to Q
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
3, 4
2.4 3.4 4.2 5.1 9.2
2.8 4.0 4.9 6.0 10.8
ns ns ns ns ns
Logic Module Sequential Timing
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency
0.5 0.0 1.3 0.0 7.4 7.4 16.4 2.5 -3.5 0.0 0.5 60
0.5 0.0 1.3 0.0 8.6 8.6 22.1 2.5 -3.5 0.0 0.5 41
ns ns ns ns ns ns ns ns ns ns ns MHz
Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
30
H iR e l F PG A s
A 12 80 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL tRD1 tRD2 tRD3 tRD4 tRD8 Pad to Y High Pad to Y Low G to Y High G to Y Low
1
`Std' Speed Min. Max. Units
Min.
Max.
4.0 3.6 6.9 6.6
4.7 4.3 8.1 7.7
ns ns ns ns
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
6.2 7.2 7.7 8.9 12.9
7.3 8.4 9.1 10.5 15.2
ns ns ns ns ns
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 0.0 0.0 8.6 13.8 13.7 16.0 73 63 6.9 7.9 6.9 7.9 0.6 3.1 0.0 0.0 8.6 13.8 16.2 18.9 62 53 13.3 17.9 13.3 18.2 8.1 9.3 8.1 9.3 0.6 3.1 15.7 21.1 15.7 21.4 ns ns ns ns ns ns ns ns MHz
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0 to 4 ns.
31
A 12 80 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description
1
`Std' Speed Min. Max. Units
Min.
Max.
TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL
Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low Delta Low to High Delta High to Low
1
11.0 13.9 12.3 16.1 9.8 11.5 12.4 15.5 0.09 0.17
13.0 16.4 14.4 19.0 11.5 13.6 14.6 18.2 0.11 0.20
ns ns ns ns ns ns ns ns ns/pF ns/pF
CMOS Output Module Timing
Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low Delta Low to High Delta High to Low
14.0 11.7 12.3 16.1 9.8 11.5 12.4 15.5 0.17 0.12
16.5 13.7 14.4 19.0 11.5 13.6 14.6 18.2 0.20 0.15
ns ns ns ns ns ns ns ns ns/pF ns/pF
Notes: 1. Delays based on 50 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.
32
H iR e l F PG A s
A 12 80 X L T i m i n g C h ar a c t er i st i c s
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description
1
`Std' Speed Min. Max. Units
Min.
Max.
Logic Module Propagation Delays tPD1 tCO tGO tRS tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Single Module
3.7 3.7 3.7 3.7
2
4.3 4.3 4.3 4.3
ns ns ns ns
Sequential Clk to Q Latch G to Q Flip-Flop (Latch) Reset to Q
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
3, 4
1.7 2.5 3.1 3.7 7.0
2.1 3.0 3.6 4.3 8.3
ns ns ns ns ns
Logic Module Sequential Timing
Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency
0.4 0.0 1.1 0.0 5.3 5.3 10.7 0.0 0.4 0.0 0.4 90
0.5 0.0 1.2 0.0 6.1 6.1 12.3 0.0 0.4 0.0 0.4 75
ns ns ns ns ns ns ns ns ns ns ns MHz
Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
33
A 12 80 X L T i m i n g C h ar a c t er i st i c s (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL tRD1 tRD2 tRD3 tRD4 tRD8 Pad to Y High Pad to Y Low G to Y High G to Y Low
1
`Std' Speed Min. Max. Units
Min.
Max.
1.5 1.7 2.8 3.7
1.7 2.1 3.3 4.3
ns ns ns ns
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
4.6 5.2 5.5 6.4 9.2
5.3 6.1 6.5 7.5 10.8
ns ns ns ns ns
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 0.0 0.0 3.6 4.6 9.1 9.8 110 100 4.3 4.8 4.3 4.8 1.1 1.1 0.0 0.0 4.2 5.3 10.7 11.8 90 85 7.1 8.0 7.0 8.0 5.3 5.7 5.3 5.7 1.2 1.2 8.4 9.5 8.3 9.5 ns ns ns ns ns ns ns ns MHz
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0 to 4 ns.
34
H iR e l F PG A s
A 12 80 X L T i m i n g C h ar a c t er i st i c s (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description
1
`Std' Speed Min. Max. Units
Min.
Max.
TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL
Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low Delta Low to High Delta High to Low
1
5.3 5.7 5.3 5.8 7.5 7.5 5.9 6.6 0.05 0.05
6.2 6.6 6.2 6.8 8.9 8.9 6.9 7.8 0.06 0.09
ns ns ns ns ns ns ns ns ns/pF ns/pF
CMOS Output Module Timing
Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low Delta Low to High Delta High to Low
6.6 4.7 5.3 5.8 7.5 7.5 5.9 6.6 0.07 0.06
7.9 5.5 6.2 6.8 8.9 8.9 6.9 7.8 0.09 0.09
ns ns ns ns ns ns ns ns ns/pF ns/pF
Notes: 1. Delays based on 50 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.
35
A 14 25 A Ti m i ng Ch a r ac t e r i s t i cs
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description
1
`Std' Speed Min. Max. Units
Min.
Max.
Logic Module Propagation Delays tPD tCO tCLR tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tHD tSUENA tHENA tWASYN tWCLKA tA fMAX
Internal Array Module Sequential Clock to Q Asynchronous Clear to Q
2
3.0 3.0 3.0
3.5 3.5 3.5
ns ns ns
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1.3 1.9 2.1 2.6 4.2
1.5 2.1 2.5 2.9 4.9
ns ns ns ns ns
Logic Module Sequential Timing Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency 0.9 0.0 0.9 0.0 3.8 3.8 7.9 125 1.0 0.0 1.0 0.0 4.4 4.4 9.3 100 ns ns ns ns ns ns ns MHz
Input Module Propagation Delays tINY tICKY tOCKY tICLRY tOCLRY Input Data Pad to Y Input Reg IOCLK Pad to Y Output Reg IOCLK Pad to Y Input Asynchronous Clear to Y Output Asynchronous Clear to Y
1, 3
4.2 7.0 7.0 7.0 7.0
4.9 8.2 8.2 8.2 8.2
ns ns ns ns ns
Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1.3 1.9 2.1 2.6 4.2
1.5 2.1 2.5 2.9 4.9
ns ns ns ns ns
Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Optimization techniques may further reduce delays by 0 to 4 ns.
36
H iR e l F PG A s
A 14 25 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
I/O Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input F-F Data Hold (w.r.t. IOCLK Pad) Input F-F Data Setup (w.r.t. IOCLK Pad) Input Data Enable Hold (w.r.t. IOCLK Pad) Input Data Enable Setup (w.r.t. IOCLK Pad) Output F-F Data Hold (w.r.t. IOCLK Pad) Output F-F Data Setup (w.r.t. IOCLK Pad) Output Data Enable Hold (w.r.t. IOCLK Pad) Output Data Enable Setup (w.r.t. IOCLK Pad)
1
0.0 2.1 0.0 8.7 1.1 1.1 0.5 2.0
0.0 2.4 0.0 10.0 1.2 1.2 0.6 2.4
ns ns ns ns ns ns ns ns
TTL Output Module Timing tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS
Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, High Slew Enable to Pad, Z to H/L, Low Slew Enable to Pad, H/L to Z, High Slew Enable to Pad, H/L to Z, Low Slew IOCLK Pad to Pad H/L, High Slew IOCLK Pad to Pad H/L, Low Slew Delta Low to High, High Slew Delta Low to High, Low Slew Delta High to Low, High Slew Delta High to Low, Low Slew
7.5 11.9 6.0 10.9 9.9 9.9 10.5 15.7 0.04 0.07 0.05 0.07
8.9 14.0 7.0 12.8 11.6 11.6 11.6 17.4 0.04 0.08 0.06 0.08
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF
Note: 1. Delays based on 35 pF loading.
37
A 14 25 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description
1
`Std' Speed Min. Max. Units
Min.
Max.
CMOS Output Module Timing tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX
Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, High Slew Enable to Pad, Z to H/L, Low Slew Enable to Pad, H/L to Z, High Slew Enable to Pad, H/L to Z, Low Slew IOCLK Pad to Pad H/L, High Slew IOCLK Pad to Pad H/L, Low Slew Delta Low to High, High Slew Delta Low to High, Low Slew Delta High to Low, High Slew Delta High to Low, Low Slew
9.2 17.3 7.7 13.1 9.9 10.5 12.5 18.1 0.06 0.11 0.04 0.05
10.8 20.3 9.1 15.5 11.6 11.6 13.7 20.1 0.07 0.13 0.05 0.06
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF
Dedicated (Hard-Wired) I/O Clock Network Input Low to High (Pad to I/O Module Input) Minimum Pulse Width High Minimum Pulse Width Low Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency 7.9 125 3.9 3.9 3.9 0.5 9.3 100 3.0 4.4 4.4 4.4 0.5 3.5 ns ns ns ns ns ns MHz
Dedicated (Hard-Wired) Array Clock Network Input Low to High (Pad to S-Module Input) Input High to Low (Pad to S-Module Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 7.9 125 3.9 3.9 0.4 9.3 100 4.6 4.6 4.4 4.4 0.4 5.3 5.3 ns ns ns ns ns ns MHz
Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.
38
H iR e l F PG A s
A 14 25 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW tRP fRMAX tIOHCKSW tIORCKSW tHRCKSW Input Low to High (FO=64) Input High to Low (FO=64) Min. Pulse Width High (FO=64) Min. Pulse Width Low (FO=64) Maximum Skew (FO=128) Minimum Period (FO=64) Maximum Frequency (FO=64) 10.1 100 4.9 4.9 1.1 11.6 85 5.5 6.0 5.7 5.7 1.2 6.4 7.0 ns ns ns ns ns ns MHz
Clock-to-Clock Skews I/O Clock to H-Clock Skew I/O Clock to R-Clock Skew H-Clock to R-Clock Skew (FO = 64) (FO = 50% max.) 0.0 0.0 0.0 0.0 3.0 3.0 1.0 3.0 0.0 0.0 0.0 0.0 3.0 3.0 1.0 3.0 ns ns ns ns
39
A 14 60 A Ti m i ng Ch a r ac t e r i s t i cs
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Logic Module Propagation Delays1 tPD tCO tCLR Internal Array Module Sequential Clock to Q Asynchronous Clear to Q
2
3.0 3.0 3.0
3.5 3.5 3.5
ns ns ns
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1.3 1.9 2.1 2.6 4.2
1.5 2.1 2.5 2.9 4.9
ns ns ns ns ns
Logic Module Sequential Timing tSUD tHD tSUENA tHENA tWASYN tWCLKA tA fMAX Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency 0.9 0.0 0.9 0.0 4.8 4.8 9.9 100 1.0 0.0 1.0 0.0 5.6 5.6 11.6 85 ns ns ns ns ns ns ns MHz
Input Module Propagation Delays tINY tICKY tOCKY tICLRY tOCLRY Input Data Pad to Y Input Reg IOCLK Pad to Y Output Reg IOCLK Pad to Y Input Asynchronous Clear to Y Output Asynchronous Clear to Y 4.2 7.0 7.0 7.0 7.0 4.9 8.2 8.2 8.2 8.2 ns ns ns ns ns
Input Module Predicted Routing Delays2, 3 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 1.3 1.9 2.1 2.6 4.2 1.5 2.1 2.5 2.9 4.9 ns ns ns ns ns
Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Optimization techniques may further reduce delays by 0 to 4 ns.
40
H iR e l F PG A s
A 14 60 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
I/O Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input F-F Data Hold (w.r.t. IOCLK Pad) Input F-F Data Setup (w.r.t. IOCLK Pad) Input Data Enable Hold (w.r.t. IOCLK Pad) Input Data Enable Setup (w.r.t. IOCLK Pad) Output F-F Data Hold (w.r.t. IOCLK Pad) Output F-F Data Setup (w.r.t. IOCLK Pad) Output Data Enable Hold (w.r.t. IOCLK Pad) Output Data Enable Setup (w.r.t. IOCLK Pad)
1
0.0 2.1 0.0 8.7 1.1 1.1 0.5 2.0
0.0 2.4 0.0 10.0 1.2 1.2 0.6 2.4
ns ns ns ns ns ns ns ns
TTL Output Module Timing tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS
Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, High Slew Enable to Pad, Z to H/L, Low Slew Enable to Pad, H/L to Z, High Slew Enable to Pad, H/L to Z, Low Slew IOCLK Pad to Pad H/L, High Slew IOCLK Pad to Pad H/L, Low Slew Delta Low to High, High Slew Delta Low to High, Low Slew Delta High to Low, High Slew Delta High to Low, Low Slew
7.5 11.9 6.0 10.9 11.5 10.9 11.6 17.8 0.04 0.07 0.05 0.07
8.9 14.0 7.0 12.8 13.5 12.8 13.4 19.8 0.04 0.08 0.06 0.08
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF
Note: 1. Delays based on 35 pF loading.
41
A 14 60 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
CMOS Output Module Timing1 tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, High Slew Enable to Pad, Z to H/L, Low Slew Enable to Pad, H/L to Z, High Slew Enable to Pad, H/L to Z, Low Slew IOCLK Pad to Pad H/L, High Slew IOCLK Pad to Pad H/L, Low Slew Delta Low to High, High Slew Delta Low to High, Low Slew Delta High to Low, High Slew Delta High to Low, Low Slew 9.2 17.3 7.7 13.1 10.9 10.9 14.1 20.2 0.06 0.11 0.04 0.05 10.8 20.3 9.1 15.5 12.8 12.8 16.0 22.4 0.07 0.13 0.05 0.06 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF
Dedicated (Hard-Wired) I/O Clock Network Input Low to High (Pad to I/O Module Input) Minimum Pulse Width High Minimum Pulse Width Low Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency 9.9 100 4.8 4.8 3.9 0.9 11.6 85 3.5 5.7 5.7 4.4 1.0 4.1 ns ns ns ns ns ns MHz
Dedicated (Hard-Wired) Array Clock Network Input Low to High (Pad to S-Module Input) Input High to Low (Pad to S-Module Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 9.9 100 4.8 4.8 0.9 11.6 85 5.5 5.5 5.7 5.7 1.0 6.4 6.4 ns ns ns ns ns ns MHz
Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.
42
H iR e l F PG A s
A 14 60 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW tRP fRMAX tIOHCKSW tIORCKSW tHRCKSW Input Low to High (FO=256) Input High to Low (FO=256) Min. Pulse Width High (FO=256) Min. Pulse Width Low (FO=256) Maximum Skew (FO=128) Minimum Period (FO=256) Maximum Frequency (FO=256) 12.9 75 6.3 6.3 1.9 14.5 65 9.0 9.0 7.1 7.1 2.1 10.5 10.5 ns ns ns ns ns ns MHz
Clock-to-Clock Skews I/O Clock to H-Clock Skew I/O Clock to R-Clock Skew H-Clock to R-Clock Skew (FO = 64) (FO = 50% max.) 0.0 0.0 0.0 0.0 3.0 5.0 1.0 3.0 0.0 0.0 0.0 0.0 3.0 5.0 1.0 3.0 ns ns ns ns
43
A 14 10 0A T i m i n g C h ar a c t er i st i c s
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Logic Module Propagation Delays1 tPD tCO tCLR Internal Array Module Sequential Clock to Q Asynchronous Clear to Q
2
3.0 3.0 3.0
3.5 3.5 3.5
ns ns ns
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1.3 1.9 2.1 2.6 4.2
1.5 2.1 2.5 2.9 4.9
ns ns ns ns ns
Logic Module Sequential Timing tSUD tHD tSUENA tHENA tWASYN tWCLKA tA fMAX Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency 1.0 0.6 1.0 0.6 4.8 4.8 9.9 100 1.0 0.6 1.0 0.6 5.6 5.6 11.6 85 ns ns ns ns ns ns ns MHz
Input Module Propagation Delays tINY tICKY tOCKY tICLRY tOCLRY Input Data Pad to Y Input Reg IOCLK Pad to Y Output Reg IOCLK Pad to Y Input Asynchronous Clear to Y Output Asynchronous Clear to Y 4.2 7.0 7.0 7.0 7.0 4.9 8.2 8.2 8.2 8.2 ns ns ns ns ns
Input Module Predicted Routing Delays2, 3 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 1.3 1.9 2.1 2.6 4.2 1.5 2.1 2.5 2.9 4.9 ns ns ns ns ns
Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Optimization techniques may further reduce delays by 0 to 4 ns.
44
H iR e l F PG A s
A 14 10 0A T i m i n g C h ar a c t er i st i c s (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
I/O Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input F-F Data Hold (w.r.t. IOCLK Pad) Input F-F Data Setup (w.r.t. IOCLK Pad) Input Data Enable Hold (w.r.t. IOCLK Pad) Input Data Enable Setup (w.r.t. IOCLK Pad) Output F-F Data Hold (w.r.t. IOCLK Pad) Output F-F Data Setup (w.r.t. IOCLK Pad) Output Data Enable Hold (w.r.t. IOCLK Pad) Output Data Enable Setup (w.r.t. IOCLK Pad)
1
0.0 2.1 0.0 8.7 1.2 1.2 0.6 2.4
0.0 2.4 0.0 10.0 1.2 1.2 0.6 2.4
ns ns ns ns ns ns ns ns
TTL Output Module Timing tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS
Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, High Slew Enable to Pad, Z to H/L, Low Slew Enable to Pad, H/L to Z, High Slew Enable to Pad, H/L to Z, Low Slew IOCLK Pad to Pad H/L, High Slew IOCLK Pad to Pad H/L, Low Slew Delta Low to High, High Slew Delta Low to High, Low Slew Delta High to Low, High Slew Delta High to Low, Low Slew
7.5 11.9 6.0 10.9 11.9 10.9 12.2 17.8 0.04 0.07 0.05 0.07
8.9 14.0 7.0 12.8 14.0 12.8 14.0 17.8 0.04 0.08 0.06 0.08
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF
Note: 1. Delays based on 35 pF loading.
45
A 14 10 0A T i m i n g C h ar a c t er i st i c s (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
CMOS Output Module Timing1 tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, High Slew Enable to Pad, Z to H/L, Low Slew Enable to Pad, H/L to Z, High Slew Enable to Pad, H/L to Z, Low Slew IOCLK Pad to Pad H/L, High Slew IOCLK Pad to Pad H/L, Low Slew Delta Low to High, High Slew Delta Low to High, Low Slew Delta High to Low, High Slew Delta High to Low, Low Slew 9.2 17.3 7.7 13.1 11.6 10.9 14.4 20.2 0.06 0.11 0.04 0.05 10.8 20.3 9.1 15.5 14.0 12.8 16.0 22.4 0.07 0.13 0.05 0.06 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF
Dedicated (Hard-Wired) I/O Clock Network tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to I/O Module Input) Minimum Pulse Width High Minimum Pulse Width Low Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency 9.9 100 4.8 4.8 3.9 0.9 11.6 85 3.5 5.7 5.7 4.4 1.0 4.1 ns ns ns ns ns ns MHz
Dedicated (Hard-Wired) Array Clock Network Input Low to High (Pad to S-Module Input) Input High to Low (Pad to S-Module Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 9.9 100 4.8 4.8 0.9 11.6 85 5.5 5.5 5.7 5.7 1.0 6.4 6.4 ns ns ns ns ns ns MHz
Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.
46
H iR e l F PG A s
A 14 10 0A T i m i n g C h ar a c t er i st i c s (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW tRP fRMAX tIOHCKSW tIORCKSW tHRCKSW Input Low to High (FO=256) Input High to Low (FO=256) Min. Pulse Width High (FO=256) Min. Pulse Width Low (FO=256) Maximum Skew (FO=128) Minimum Period (FO=256) Maximum Frequency (FO=256) 12.9 75 6.3 6.3 1.9 14.5 65 9.0 9.0 7.1 7.1 2.1 10.5 10.5 ns ns ns ns ns ns MHz
Clock-to-Clock Skews I/O Clock to H-Clock Skew I/O Clock to R-Clock Skew H-Clock to R-Clock Skew (FO = 64) (FO = 50% max.) 0.0 0.0 0.0 0.0 3.5 5.0 1.0 3.0 0.0 0.0 0.0 0.0 3.5 5.0 1.0 3.0 ns ns ns
47
A 32 10 0D X T i m i ng C ha r a ct er i s t i c s
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Logic Module Combinatorial Functions tPD tPDD tRD1 tRD2 tRD3 tRD4 tRD5 tRDD tCO tGO tSU tH tRO tSUENA tHENA tWCLKA tWASYN Internal Array Module Delay Internal Decode Module Delay
1
3.1 3.3
4.1 4.3
ns ns
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1.3 1.9 2.6 3.3 0.6 0.5
1.8 2.6 3.4 4.3 0.8 0.6
ns ns ns ns ns ns
Decode-to-Output Routing Delay
Logic Module Sequential Timing Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Setup Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset to Output Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.9 0.0 4.3 5.6 0.5 0.0 3.1 1.2 0.0 5.8 7.5 3.1 3.1 0.6 0.0 4.1 4.1 4.1 ns ns ns ns ns ns ns ns ns
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
48
H iR e l F PG A s
A 32 10 0D X T i m i ng C ha r a ct er i s t i c s (continued)
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
'-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Synchronous SRAM Operations tRC tWC tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Read Cycle Time Write Cycle Time Clock High/Low Time Data Valid After Clock High/Low Address/Data Setup Time Address/Data Hold Time Read Enable Setup Read Enable Hold Write Enable Setup Write Enable Hold Block Enable Setup Block Enable Hold 2.1 0.0 0.8 4.4 3.5 0.0 3.6 0.0 8.8 8.8 4.4 4.4 2.8 0.0 1.1 5.9 4.7 0.0 4.8 0.0 11.8 11.8 5.9 5.9 ns ns ns ns ns ns ns ns ns ns ns ns
Asynchronous SRAM Operations Asynchronous Access Time Read Address Valid Address/Data Setup Time Address/Data Hold Time Read Enable Setup to Address Valid Read Enable Hold Write Enable Setup Write Enable Hold Data Out Hold Time 11.5 2.1 0.0 0.8 4.4 3.5 0.0 1.6 10.6 15.3 2.8 0.0 1.1 5.9 4.7 0.0 2.1 14.1 ns ns ns ns ns ns ns ns ns
49
A 32 10 0D X T i m i ng C ha r a ct er i s t i c s (continued)
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fHMAX Input Data Pad to Y Input Latch Gate-to-Output Input Latch Hold Input Latch Setup Latch Active Pulse Width
1
1.9 4.0 0.0 0.7 6.1 0.0 0.9 8.1
2.6 5.3
ns ns ns ns ns
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
2.2 2.8 3.5 3.5 5.6
2.9 3.8 4.7 4.7 7.5
ns ns ns ns ns
Global Clock Network Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period (1/fmax) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 0.0 0.0 3.0 3.8 7.1 7.9 140 126 4.1 4.6 4.1 4.6 1.8 1.8 0.0 0.0 4.0 5.1 9.5 10.5 105 95 6.5 7.9 6.6 8.8 5.5 6.1 5.5 6.1 2.4 2.4 8.7 10.6 8.8 11.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0 to 4 ns.
50
H iR e l F PG A s
A 32 10 0D X T i m i ng C ha r a ct er i s t i c s (continued)
(Worst-Case Military Conditions, V C C = 4.5V, T J = 125C)
`-1' Speed Parameter Description
1
`Std' Speed Min. Max. Units
Min.
Max.
TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL tWDO tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL tWDO
Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low I/O Latch Output Setup I/O Latch Output Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad) 32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide Decode Output 0.4 0.0
5.1 6.3 6.6 7.1 11.5 11.5 11.5 12.4 0.5 0.0 11.5 16.3 0.04 0.06 0.05
6.8 8.3 8.8 9.4 15.3 15.3 15.3 16.6
ns ns ns ns ns ns ns ns ns ns
15.4 21.7 0.06 0.08 0.07
ns ns ns/pF ns/pF ns
CMOS Output Module Timing1 Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low I/O Latch Setup I/O Latch Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad) 32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide Decode Output 0.4 0.0 13.7 19.2 0.06 0.05 0.05 6.3 5.1 6.6 7.1 11.5 11.5 11.5 12.4 0.5 0.0 18.2 25.6 0.08 0.07 0.07 8.3 6.8 8.8 9.4 15.3 15.3 15.3 16.6 ns ns ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF ns
Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.
51
A 32 20 0D X T i m i ng C ha r a ct er i s t i c s
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Logic Module Combinatorial Functions tPD tPDD tRD1 tRD2 tRD3 tRD4 tRD5 tRDD tCO tGO tSU tH tRO tSUENA tHENA tWCLKA tWASYN Internal Array Module Delay Internal Decode Module Delay
1
2.8 3.4
3.8 4.6
ns ns
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
1.6 2.3 2.9 3.5 6.2 0.8
2.1 3.1 3.9 4.7 8.2 1.1
ns ns ns ns ns ns
Decode-to-Output Routing Delay
Logic Module Sequential Timing Characteristics Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Setup Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset to Output Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width 0.9 0.0 4.3 5.7 0.5 0.0 3.2 1.2 0.0 5.8 7.6 3.2 2.8 0.6 0.0 4.2 4.2 3.8 ns ns ns ns ns ns ns ns ns
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
52
H iR e l F PG A s
A 32 20 0D X T i m i ng C ha r a ct er i s t i c s (continued)
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Synchronous SRAM Operations tRC tWC tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Read Cycle Time Write Cycle Time Clock High/Low Time Data Valid After Clock High/Low Address/Data Setup Time Address/Data Hold Time Read Enable Setup Read Enable Hold Write Enable Setup Write Enable Hold Block Enable Setup Block Enable Hold 2.1 0.0 0.8 4.4 3.5 0.0 3.6 0.0 8.8 8.8 4.4 4.4 2.8 0.0 1.1 5.9 4.7 0.0 4.8 0.0 11.8 11.8 5.9 5.9 ns ns ns ns ns ns ns ns ns ns ns ns
Asynchronous SRAM Operations Asynchronous Access Time Read Address Valid Address/Data Setup Time Address/Data Hold Time Read Enable Setup to Address Valid Read Enable Hold Write Enable Setup Write Enable Hold Data Out Hold Time 11.5 2.1 0.0 0.8 4.4 3.5 0.0 1.6 10.6 15.3 2.8 0.0 1.1 5.9 4.7 0.0 2.1 14.1 ns ns ns ns ns ns ns ns ns
53
A 32 20 0D X T i m i ng C ha r a ct er i s t i c s (continued)
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25 C)
`-1' Speed Parameter Description Min. Max.
`Std' Speed Min. Max. Units
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA tIRD1 tIRD2 tIRD3 tIRD4 tIRD5 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fHMAX Input Data Pad to Y Input Latch Gate-to-Output Input Latch Hold Input Latch Setup Latch Active Pulse Width
1
1.9 4.6 0.0 0.7 6.1 0.0 0.9 8.1
2.6 6.0
ns ns ns ns ns
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
2.6 3.4 4.6 5.4 7.0
3.5 4.6 6.1 7.2 9.3
ns ns ns ns ns
Global Clock Network Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period (1/fmax) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 FO=32 FO=635 0.0 0.0 3.0 3.8 5.8 6.8 172 147 3.2 3.9 3.2 3.9 1.8 1.8 0.0 0.0 4.0 5.1 7.7 9.1 130 110 7.3 8.5 7.2 9.3 4.3 5.2 4.3 5.2 2.4 2.4 9.8 11.3 9.6 12.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz
Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0 to 4 ns.
54
H iR e l F PG A s
A 32 20 0D X T i m i ng C ha r a ct er i s t i c s (continued)
(Worst-Case Military Conditions, V C C = 4.5V, T J = 125C)
`-1' Speed Parameter Description
1
`Std' Speed Min. Max. Units
Min.
Max.
TTL Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL tWDO tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLH tLCO tACO dTLH dTHL tWDO
Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low I/O Latch Output Setup I/O Latch Output Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad) 32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide Decode Output 0.4 0.0
5.1 6.3 6.6 7.1 11.5 11.5 11.5 12.3 0.5 0.0 11.5 16.3 0.04 0.06 0.05
6.8 8.3 8.8 9.5 15.3 15.3 15.3 16.5
ns ns ns ns ns ns ns ns ns ns
15.4 21.7 0.06 0.08 0.07
ns ns ns/pF ns/pF ns
CMOS Output Module Timing1 Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low I/O Latch Setup I/O Latch Hold I/O Latch Clock-Out (Pad-to-Pad) 32 I/O Array Latch Clock-Out (Pad-to-Pad) 32 I/O Capacitive Loading, Low to High Capacitive Loading, High to Low Hard-Wired Wide Decode Output 0.4 0.0 13.7 19.2 0.06 0.05 0.05 5.1 6.3 6.6 7.1 11.5 11.5 11.5 12.3 0.5 0.0 18.2 25.6 0.08 0.07 0.07 6.8 8.3 8.8 9.5 15.3 15.3 15.3 16.5 ns ns ns ns ns ns ns ns ns ns ns ns ns/pF ns/pF ns
Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at http://www.actel.com/appnotes.
55
Pi n D es c ri pt i on
CLK Clock (Input) MODE Mode (Input)
ACT 1 only. TTL Clock input for global clock distribution network. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O.
CLKA Clock A (Input)
ACT 2, 1200XL, 3200DX, and ACT 3 only. TTL Clock input for global clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O.
CLKB Clock B (Input)
The MODE pin controls the use of diagnostic pins (DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the special functions are active. When the MODE pin is LOW, the pins function as I/Os. To provide debugging capability, the MODE pin should be terminated to GND through a 10 k resistor so that the MODE pin can be pulled high when required.
NC No Connection
This pin is not connected to circuitry within the device.
PRA, I/O Probe A (Output)
ACT 2, 1200XL, 3200DX, and ACT 3 only. TTL Clock input for global clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O.
DCLK Diagnostic Clock (Input)
TTL Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW.
GND Ground
The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW.
PRB, I/O Probe B (Output)
LOW supply voltage.
HCLK Dedicated (Hard-wired) Array Clock (Input)
ACT 3 only. TTL Clock input for sequential modules. This input is directly wired to each S-module and offers clock speeds independent of the number of S-modules being driven. This pin can also be used as an I/O.
I/O Input/Output (Input, Output)
I/O pin functions as an input, output, tristate, or bi-directional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. In the ACT 3 and 3200DX families, unused I/Os are automatically tri-stated. With this configuration, the input buffer internal to the I/O module is disabled. In the ACT 1, ACT 2 and 1200XL families, unused I/Os are automatically configured as bi-directional buffers where each buffer is configured as a LOW driver.
IOCLK Dedicated (Hard-wired) I/O Clock (Input)
The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW.
SDI Serial Data Input (Input)
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW.
VCC 5.0V Supply Voltage
HIGH supply voltage.
QCLKA/B,C,D Quadrant Clock (Input/Output)
ACT 3 only. TTL Clock input for I/O modules. This input is directly wired to each I/O module and offers clock speeds independent of the number of I/O modules being driven. This pin can also be used as an I/O.
IOPCL Dedicated (Hard-wired) I/O Preset/Clear (Input)
3200DX only. These four pins are the quadrant clock inputs. When not used as a register control signal, these pins can function as general purpose I/O.
TCK Test Clock
ACT 3 only. TTL input for I/O preset or clear. This global input is directly wired to the preset and clear inputs of all I/O registers. This pin functions as an I/O when no I/O preset or clear macros are used.
Clock signal to shift the JTAG data into the device. This pin functions as an I/O when the JTAG fuse is not programmed. JTAG pins are only available in the 3200DX device.
56
H iR e l F PG A s
TDI
Test Data In
Serial data input for JTAG instructions and data. Data is shifted in on the rising edge of TCLK. This pin functions as an I/O when the JTAG fuse is not programmed. JTAG pins are only available in the 3200DX device.
TDO Test Data Out
Serial data output for JTAG instructions and test data. This pin functions as an I/O when the JTAG fuse is not programmed. JTAG pins are only available in the 3200DX device.
TMS Test Mode Select
Serial data input for JTAG test mode. Data is shifted in on the rising edge of TCLK. This pin functions as an I/O when the JTAG fuse is not programmed. JTAG pins are only available in the 3200DX device.
57
Pa c ka ge P i n A s si g nm e n t s
84- Pi n CP GA (T op Vie w)
1 A B C D E F G H J K L 1
2
3
4
5
6
7
8
9
10 11 A B C D E
84-Pin CPGA
F G H J K L
2
3
4
5
6
7
8
9
10 11
Orientation Pin (C3)
58
H iR e l F PG A s
84- Pi n CP GA
Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C5 C6 C7 C10 C11 D1 D2 D10 D11 E1 E2 E3 E9 E10 E11 F1 F2 F3
A1010B Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O NC NC I/O I/O VCC I/O GND I/O I/O PRB, I/O SDI, I/O NC NC I/O I/O I/O DCLK, I/O NC I/O I/O NC NC I/O GND GND VCC VCC MODE VCC I/O I/O
A1020B Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O I/O NC I/O I/O VCC I/O GND I/O I/O PRB, I/O SDI, I/O I/O I/O I/O I/O I/O DCLK, I/O I/O I/O I/O I/O I/O I/O GND GND VCC VCC MODE VCC I/O I/O
Pin Number F9 F10 F11 G1 G2 G3 G9 G10 G11 H1 H2 H10 H11 J1 J2 J5 J6 J7 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
A1010B Function CLK, I/O GND I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O NC I/O I/O I/O NC I/O NC VCC I/O I/O GND I/O VCC I/O I/O NC NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
A1020B Function CLK, I/O GND I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
59
Pa c ka ge P i n A s si g nm e n t s (continued)
132- P in CP GA (T op Vi ew)
1 A B C D E F G H J K L M N 1
2
3
4
5
6
7
8
9
10 11 12 13 A B C D E F
132-Pin CPGA
G H J K L M N
2
3
4
5
6
7
8
9
10 11 12 13 Orientation Pin
60
H iR e l F PG A s
132- P in CP GA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D6 D7 A1240A Function MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND CLKB, I/O CLKA, I/O PRA, I/O GND I/O I/O SDI, I/O I/O I/O I/O DCLK, I/O I/O GND PRB, I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCC Pin Number D8 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F4 F10 F11 F12 F13 G1 G2 G3 G4 G10 G11 G12 G13 H1 H2 H3 H4 H10 H11 H12 H13 J1 J2 J3 J11 J12 J13 K1 K2 K3 K6 A1240A Function I/O I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC VCC VCC VCC VCC VCC VCC I/O I/O I/O I/O I/O I/O I/O GND I/O GND GND GND I/O I/O I/O I/O I/O I/O Pin Number K7 K8 K11 K12 K13 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 A1240A Function VCC I/O I/O GND I/O I/O I/O I/O I/O GND I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
61
Pa c ka ge P i n A s si g nm e n t s (continued)
133- P in CP GA (T op Vi ew)
1 A B C D E F G H J K L M N 1
2
3
4
5
6
7
8
9
10 11 12 13 A B C D E F
133-Pin CPGA
G H J K L M N
2
3
4
5
6
7
8
9
10 11 12 13 Orientation Pin
62
H iR e l F PG A s
133- P in CP GA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D4 D6 D7 A1425A Function NC GND I/O I/O I/O PRA, I/O NC I/O I/O I/O I/O I/O NC I/O VCC I/O I/O I/O CLKB, I/O VCC I/O I/O I/O I/O VCC I/O I/O SDI, I/O GND I/O I/O I/O GND I/O I/O IOCLK, I/O GND GND I/O I/O I/O I/O DCLK, I/O CLKA, I/O I/O Pin Number D8 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F4 F10 F11 F12 F13 G1 G2 G3 G4 G10 G11 G12 G13 H1 H2 H3 H4 H10 H11 H12 H13 J1 J2 J3 J11 J12 J13 K1 K2 K3 K6 K7 A1425A Function I/O I/O I/O I/O I/O I/O MODE VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O NC VCC GND I/O I/O GND VCC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O VCC I/O I/O I/O I/O I/O HCLKA, I/O Pin Number K8 K11 K12 K13 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 A1425A Function I/O I/O I/O I/O I/O I/O GND I/O I/O PRB, I/O GND I/O I/O IOPCL, I/O GND I/O I/O I/O VCC GND I/O I/O I/O VCC I/O I/O I/O I/O VCC I/O NC I/O I/O I/O I/O I/O NC I/O I/O I/O I/O GND NC
63
Pa c ka ge P i n A s si g nm e n t s (continued)
176- P in CP GA (T op Vi ew)
1 A B C D E F G H J K L M N P R 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 A B C D E F G
176-Pin CPGA
H J K L M N P R
2
3
4
5
6
7
8
9
10 11 12 13 14 15
.
64
H iR e l F PG A s
176- P in CP GA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 A1280A Function I/O I/O I/O I/O I/O I/O I/O I/O CLKA, I/O I/O I/O I/O I/O I/O I/O I/O I/O DCLK, I/O I/O I/O I/O I/O CLKB, I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O MODE I/O I/O I/O I/O GND PRA, I/O I/O I/O I/O I/O I/O A1280XL Function I/O I/O I/O I/O I/O I/O I/O I/O CLKA, I/O I/O I/O I/O I/O I/O I/O I/O I/O DCLK, I/O I/O I/O I/O I/O CLKB, I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O MODE I/O I/O I/O I/O GND PRA, I/O I/O I/O I/O I/O I/O Pin Number C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E1 E2 E3 E4 E12 E13 E14 E15 F1 F2 F3 F4 F12 F13 F14 F15 G1 G2 G3 G4 G12 G13 G14 G15 H1 H2 H3 H4 A1280A Function I/O I/O I/O I/O GND VCC GND PRB, I/O VCC I/O GND VCC GND I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O VCC VCC GND A1280XL Function I/O I/O I/O I/O GND VCC GND PRB, I/O VCC I/O GND VCC GND I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O VCC VCC GND
65
176- P in CP GA (C ont inu ed) Pin Number H12 H13 H14 H15 J1 J2 J3 J4 J12 J13 J14 J15 K1 K2 K3 K4 K12 K13 K14 K15 L1 L2 L3 L4 L12 L13 L14 L15 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 N1 A1280A Function GND VCC VCC I/O I/O I/O I/O VCC GND GND VCC I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O GND VCC GND I/O GND I/O GND VCC GND I/O I/O I/O I/O A1280XL Function GND VCC VCC I/O I/O I/O I/O VCC GND GND VCC I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O GND VCC GND I/O GND I/O GND VCC GND I/O I/O I/O I/O Pin Number N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 A1280A Function I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A1280XL Function I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
66
H iR e l F PG A s
Pa c ka ge P i n A s si g nm e n t s (continued)
207- P in CP GA (T op Vi ew)
1 A B C D E F G H J K L M N P R S T 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 A B C D E F G
207-Pin CPGA
H J K L M N P R S T
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
67
207- P in CP GA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 A1460A Function NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC VCC I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O VCC NC NC NC SDI, I/O I/O I/O I/O I/O I/O I/O Pin Number C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E14 E15 E16 E17 F1 F2 F3 F4 F14 F15 F16 F17 G1 G2 A1460A Function I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND GND I/O MODE I/O GND I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O DCLK, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O . Pin Number G3 G4 G14 G15 G16 G17 H1 H2 H3 H4 H14 H15 H16 H17 J1 J2 J3 J4 J14 J15 J16 J17 K1 K2 K3 K4 K14 K15 K16 K17 L1 L2 L3 L4 L14 L15 L16 L17 M1 M2 M3 M4 M14 A1460A Function I/O I/O I/O I/O I/O I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC CLKB, I/O GND GND HCLK, I/O VCC I/O CLKA, I/O I/O I/O I/O I/O I/O PRB, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
68
H iR e l F PG A s
207- P in CP GA (C ont inu ed) Pin Number M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 A1460A Function I/O I/O I/O I/O I/O I/O I/O IOPCL, I/O I/O I/O I/O I/O I/O GND GND IOCLK, I/O I/O GND I/O GND I/O I/O VCC I/O GND I/O I/O Pin Number P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 S1 S2 S3 S4 S5 S6 S7 S8 S9 A1460A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O NC VCC NC I/O I/O I/O I/O I/O VCC Pin Number S10 S11 S12 S13 S14 S15 S16 S17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 A1460A Function I/O I/O I/O I/O I/O I/O VCC NC NC NC I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC
69
Pa c ka ge P i n A s si g nm e n t s (continued)
257- P in CP GA (T op Vi ew)
1 A B C D E F G H J K L M N P R T V X Y 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 A B C D E F G H 257-Pin CPGA J K L M N P R T V X Y
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
70
H iR e l F PG A s
257- P in CP GA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 A14100A Function I/O I/O I/O I/O MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC GND I/O I/O Pin Number C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E7 E9 E11 E13 E16 E17 E18 A14100A Function I/O I/O I/O VCC I/O I/O VCC I/O I/O I/O VCC I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O DCLK, I/O NC I/O I/O GND I/O I/O I/O I/O Pin Number E19 F1 F2 F3 F4 F16 F17 F18 F19 G1 G2 G3 G4 G5 G15 G16 G17 G18 G19 H1 H2 H3 H4 H16 H17 H18 H19 J1 J2 J3 J4 J5 J15 J16 J17 J18 J19 K1 K2 K3 K4 K16 K17 K18 A14100A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O I/O I/O I/O GND I/O HCLK, I/O PRB, I/O I/O I/O I/O I/O VCC GND GND VCC I/O
71
257- P in CP GA (C ont inu ed) Pin Number K19 L1 L2 L3 L4 L5 L15 L16 L17 L18 L19 M1 M2 M3 M4 M16 M17 M18 M19 N1 N2 N3 N4 N5 N15 N16 N17 N18 N19 P1 P2 P3 P4 P16 P17 P18 P19 R1 R2 R3 R4 R7 A14100A Function I/O I/O I/O I/O CLKA, I/O CLKB, I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O Pin Number R9 R11 R13 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 A14100A Function I/O I/O I/O IOPCL, I/O I/O I/O I/O I/O I/O I/O GND IOCLK, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O VCC I/O I/O I/O VCC I/O I/O VCC I/O I/O I/O I/O I/O I/O Pin Number V17 V18 V19 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 A14100A Function VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
72
H iR e l F PG A s
Pa c ka ge P i n A s si g nm e n t s (continued)
84- Pi n CQFP (To p V iew )
Pin #1 Index
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
84-Pin CQFP
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
73
84- Pi n CQFP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A1020B Function NC I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O VCC VCC I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O
A32100DX Function GND MODE I/O I/O I/O I/O VCC I/O I/O GND VCC VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O (WD) I/O (WD) I/O QCLKA, I/O GND I/O (WD) I/O GND VCC I/O (WD) I/O (WD) QCLKB, I/O I/O (WD) GND I/O (WD) I/O (WD) I/O (WD) SDO, I/O
Pin Number 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
A1020B Function I/O I/O I/O I/O I/O I/O GND GND I/O I/O CLKA, I/O I/O MODE VCC VCC I/O I/O I/O SDI, I/O DCLK, I/O PRA, I/O PRB, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O
A32100DX Function GND I/O I/O I/O I/O I/O I/O GND TCK, I/O GND VCC VCC VCC VCC I/O I/O GND I/O I/O I/O GND SDI, I/O I/O (WD) I/O (WD) I/O (WD) I/O (WD) QCLKD, I/O I/O (WD) I/O (WD) PRA, I/O CLKA, I/O VCC GND CLKB, I/O PRB, I/O I/O (WD) I/O (WD) QCLKC, I/O GND I/O (WD) I/O (WD) DCLK, I/O
74
H iR e l F PG A s
Pa c ka ge P i n A s si g nm e n t s (continued)
132- P in CQF P (T op Vie w)
132 131 130 129 128 127 126 125 124
107 106 105 104 103 102 101 100
Pin #1 Index
1 2 3 4 5 6 7 8
99 98 97 96 95 94 93 92
132-Pin CQFP
25 26 27 28 29 30 31 32 33 75 74 73 72 71 70 69 68 67
34 35 36 37 38 39 40 41 42
59 60 61 62 63 64 65 66
75
132- P in CQF P Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 A1425A Function NC GND SDI, I/O I/O I/O I/O I/O I/O MODE GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O NC I/O GND I/O I/O I/O I/O I/O GND VCC I/O Pin Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 A1425A Function I/O I/O I/O PRB, I/O I/O HCLK, I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O IOPCL, I/O GND NC NC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 A1425A Function VCC GND VCC GND I/O I/O I/O I/O I/O IOCLK, I/O NC NC GND I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O CLKA, I/O CLKB, I/O PRA, I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O DCLK, I/O NC
76
H iR e l F PG A s
Pa c ka ge P i n A s si g nm e n t s (continued)
172- P in CQF P (T op Vie w)
172 171 170 169 168 167 166 165 164
137 136 135 134 133 132 131 130
Pin #1 Index
1 2 3 4 5 6 7 8
129 128 127 126 125 124 123 122
172-Pin CQFP
35 36 37 38 39 40 41 42 43 95 94 93 92 91 90 89 88 87
44 45 46 47 48 49 50 51 52
79 80 81 82 83 84 85 86
77
172- P in CQF P Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 A1280A Function MODE I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCC VCC I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O A1280XL Function MODE I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCC VCC I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O Pin Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 A1280A Function I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O A1280XL Function I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O
78
H iR e l F PG A s
172- P in CQF P (Co nti nue d) Pin Number 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 A1280A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O GND VCC GND VCC VCC I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O A1280XL Function I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O GND VCC GND VCC VCC I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O Pin Number 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 A1280A Function SDI, I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O PRA, I/O I/O CLKA, I/O VCC GND I/O CLKB, I/O I/O PRB, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O DCLK, I/O I/O A1280XL Function SDI, I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O PRA, I/O I/O CLKA, I/O VCC GND I/O CLKB, I/O I/O PRB, I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O DCLK, I/O I/O
79
Pa c ka ge P i n A s si g nm e n t s (continued)
196- P in CQF P (T op Vie w)
196 195 194 193 192 191 190 189 188
155 154 153 152 151 150 149 148
Pin #1 Index
1 2 3 4 5 6 7 8
147 146 145 144 143 142 141 140
196-Pin CQFP
41 42 43 44 45 46 47 48 49 107 106 105 104 103 102 101 100 99
50 51 52 53 54 55 56 57 58
91 92 93 94 95 96 97 98
80
H iR e l F PG A s
196- P in CQF P Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A1460A Function GND SDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O MODE VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC VCC I/O I/O I/O I/O Pin Number 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 A1460A Function I/O I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O HCLK, I/O I/O I/O I/O I/O I/O I/O I/O I/O GND Pin Number 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 A1460A Function I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O GND I/O IOPCL, I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCC VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
81
196- P in CQF P (Co nti nue d) Pin Number 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 A1460A Function I/O I/O I/O I/O I/O I/O I/O VCC GND GND VCC I/O I/O I/O I/O I/O I/O I/O IOCLK, I/O GND I/O I/O I/O Pin Number 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 A1460A Function I/O I/O VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA, I/O CLKB, I/O PRA, I/O I/O Pin Number 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 A1460A Function I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCC I/O I/O I/O GND I/O I/O DCLK, I/O
82
H iR e l F PG A s
Pa c ka ge P i n A s si g nm e n t s (continued)
208- P in CQF P (T op Vie w)
208 207 206 205 204 203 202 201 200
164 163 162 161 160 159 158 157
Pin #1 Index
1 2 3 4 5 6 7 8
156 155 154 153 152 151 150 149
208-Pin CQFP
44 45 46 47 48 49 50 51 52 113 112 111 110 109 108 107 106 105
53 54 55 56 57 58 59 60 61
97 98 99 100 101 102 103 104
83
208- P in CQF P Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A32100DX Function GND VCC MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCC VCC I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 A32100DX Function I/O I/O I/O I/O I/O I/O I/O I/O GND GND TMS, I/O TDI, I/O I/O I/O (WD) I/O (WD) I/O VCC I/O I/O I/O I/O QCLKA, I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O I/O I/O GND VCC VCC I/O I/O I/O I/O I/O (WD) I/O (WD) Pin Number 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 A32100DX Function I/O I/O I/O I/O QCLKB, I/O I/O I/O (WD) I/O (WD) I/O I/O I/O VCC I/O I/O (WD) I/O (WD) I/O SDO, I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O TCK, I/O GND
84
H iR e l F PG A s
208- P in CQF P (Co nti nue d) Pin Number 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 A32100DX Function VCC GND VCC VCC I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O Pin Number 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 A32100DX Function GND I/O SDI, I/O I/O I/O (WD) I/O (WD) I/O VCC I/O I/O I/O I/O (WD) I/O (WD) I/O QCLKD, I/O I/O I/O I/O I/O I/O (WD) I/O (WD) PRA, I/O I/O CLKA, I/O I/O VCC VCC Pin Number 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A32100DX Function GND I/O CLKB, I/O I/O PRB, I/O I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD) QCLKC, I/O I/O I/O I/O I/O I/O VCC I/O (WD) I/O (WD) I/O I/O DCLK, I/O I/O
85
Pa c ka ge P i n A s si g nm e n t s (continued)
256- P in CQF P (T op Vie w)
256 255 254 253 252 251 250 249 248
200 199 198 197 196 195 194 193
Pin #1 Index
1 2 3 4 5 6 7 8
192 191 190 189 188 187 186 185
256-Pin CQFP
56 57 58 59 60 61 62 63 64 137 136 135 134 133 132 131 130 129
65 66 67 68 69 70 71 72 73
121 122 123 124 125 126 127 128
86
H iR e l F PG A s
256- P in CQF P Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 A14100A Function GND SDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O MODE I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A32200DX Function NC GND I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O VCC VCC GND VCC GND TCK, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 A14100A Function I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A32200DX Function I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND GND NC NC NC I/O SDO, I/O I/O I/O (WD) I/O (WD) I/O VCC I/O I/O I/O I/O (WD) GND I/O (WD) I/O QCLKB, I/O I/O I/O I/O I/O I/O I/O I/O (WD) I/O (WD) Pin Number 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 A14100A Function I/O PRB, I/O GND VCC GND VCC I/O HCLK, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOPCL, I/O GND I/O I/O I/O I/O A32200DX Function I/O I/O I/O I/O I/O I/O VCC VCC GND GND I/O I/O I/O I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD) I/O QCLKA, I/O I/O GND I/O I/O I/O I/O VCC I/O I/O (WD) I/O (WD) I/O I/O TDI, I/O TMS, I/O GND NC NC NC GND I/O
87
256- P in CQF P (Co nti nue d) Pin Number 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 A14100A Function I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC A32200DX Function I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O VCC VCC GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O Pin Number 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 A14100A Function GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOCLK, I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A32200DX Function I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O MODE VCC GND NC NC NC I/O DCLK, I/O I/O I/O I/O I/O (WD) I/O (WD) VCC I/O I/O I/O I/O GND I/O I/O QCLKC, I/O I/O I/O (WD) I/O (WD) I/O I/O I/O (WD) I/O (WD) Pin Number 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 A14100A Function I/O I/O CLKA, I/O CLKB, I/O VCC GND VCC GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DCLK, I/O A32200DX Function I/O PRB, I/O I/O CLKB, I/O I/O GND GND VCC VCC I/O CLKA, I/O I/O PRA, I/O I/O I/O I/O (WD) I/O (WD) I/O I/O I/O I/O I/O I/O QCLKD, I/O I/O I/O (WD) GND I/O (WD) I/O I/O I/O VCC I/O I/O (WD) I/O (WD) I/O SDI, I/O I/O GND NC
88
H iR e l F PG A s
Pa c ka ge M e ch an i c al D r a w i ng s
84- Pi n CP GA
.050" .010" Pin #1 ID .045 .055
0.18" .002"
.100" BSC
1.100" .020" square
.080" .110"
.120" .140"
L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 1.000 BSC
Orientation Pin
Notes: 1. All dimensions are in inches unless otherwise stated. 2. BSC--Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
89
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
132-Pin CPGA
.085" .110"
Pin #1 ID
.045 .055 0.18" .002"
.100" BSC
.050" .010" 1.360" .015" square .120" .140"
N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 1.200 BSC
Orientation Pin
Notes: 1. All dimensions are in inches unless otherwise stated. 2. BSC--Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
90
H iR e l F PG A s
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
133- P in CP GA
Top View
Pin #1
0.100" 0.130"
0.045" 0.055" 0.018" 0.002"
0.100" BSC
0.050" 0.010" 1.360" 0.015" square 0.120" 0.140"
N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 1.200" BSC
Side View
Orientation Pin
Bottom View
Notes: 1. All dimensions are in inches unless otherwise stated. 2. BSC--Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
91
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
176- P in CP GA
INDEX MARK 0.102" 0.132"
0.100" BSC
0.018" .002"
0.050" .005" 1.570" .015" square 0.120" 0.140"
R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1.400 BSC
Notes: 1. All dimensions are in inches unless otherwise stated. 2. BSC--Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
92
H iR e l F PG A s
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
207- P in CP GA
Top View
INDEX MARK 0.120" 0.015"
0.100" BSC
0.018" 0.002"
0.05" 0.005"
1.77" 0.010" square
0.180" 0.010" 0.05" 0.005"
U T R P N M L K J H G F E D C B A
Side View
1.600" BSC
1
2
3
4
5
6
7
8
9
10 11 12 13
14
15
16
17
Bottom View
Notes: 1. All dimensions are in inches unless otherwise stated. 2. BSC--Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
93
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
257- P in CP GA
Top View
0.105" 0.012"
0.100" BSC
0.018" 0.002"
0.05" 0.005"
1.970" 0.015" square
0.180" 0.010" 0.05" 0.01"
Y X V T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Side View
1.800" BSC
Bottom View
Notes: 1. All dimensions are in inches unless otherwise stated. 2. BSC--Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
94
H iR e l F PG A s
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
84- Pi n CQFP
Top View D1 D2
H
E2
E1
F
e L1
b
Side View A Lid
c A1
Notes: 1. Seal ring and lid are connected to Ground. 2. Lead material is Kovar with minimum 50 microinches gold plate over nickel. 3. Packages are shipped unformed with the ceramic tie bar in a test carrier.
95
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
132-Pin, 172-Pin, 196-Pin, 208-Pin, and 256-Pin CQFP (Cavity Up)
Top View H D1 D2
No. 1 Ceramic Tie Bar
L1
E2
E1
K
F e b
Side View Lid A
A1
C Lead Kovar
Notes: 1. Outside leadframe holes (from dimension H) are circular for the CQ208 and CQ256. 2. Seal ring and lid are connected to Ground. 3. Lead material is Kovar with minimum 50 microinches gold plate over nickel. 4. Packages are shipped unformed with the ceramic tie bar. 5. 32200DX - CQ208 has a heat sink on the back.
96
H iR e l F PG A s
CQFP (Ce ram i c Q uad Fla t Pa ck)
CQFP 84 Symbol A A1 b c D1/E1 D2/E2 e F H K L1 1.595 0.130 Min. 0.070 0.060 0.008 0.004 0.640 Nom. 0.090 0.075 0.010 0.006 0.650 0.500 BSC 0.025 BSC 0.140 1.460 BSC -- 1.600 1.615 2.485 0.150 0.325 Max. 0.100 0.080 0.012 0.008 0.660 Min. 0.094 0.080 0.007 0.004 0.940
CQFP 132 Nom. 0.105 0.090 0.008 0.006 0.950 0.800 BSC 0.025 BSC 0.350 2.320 BSC 2.140 BSC 2.500 2.505 2.485 0.375 0.175 Max. 0.116 0.100 0.010 0.008 0.960 Min. 0.094 0.080 0.007 0.004 1.168
CQFP 172 Nom. 0.105 0.090 0.008 0.006 1.180 1.050 BSC 0.025 BSC 0.200 2.320 BSC 2.140 BSC 2.495 2.505 2.485 0.225 0.175 Max. 0.116 0.100 0.010 0.008 1.192 Min. 0.094 0.080 0.007 0.004 1.336
CQFP 196 Nom. 0.105 0.090 0.008 0.006 1.350 1.200 BSC 0.025 BSC 0.200 2.320 BSC 2.140 BSC 2.495 2.505 0.225 Max. 0.116 0.100 0.010 0.008 1.364
Note: 1. All dimensions are in inches except CQ208 and CQ256, which are in millimeters. 2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
CQFP (Ce ram i c Q uad Fla t Pa ck)
CQFP 208 Symbol A A1 b c D1/E1 D2/E2 e F H K L1 74.60 7.05 Min. 2.78 2.43 0.18 0.11 28.96 Nom. 3.17 2.79 0.20 0.15 29.21 25.5 BSC 0.50 BSC 7.75 70.00 BSC 65.90 BSC 75.00 75.40 74.60 8.45 7.05 Max. 3.56 3.15 0.22 0.17 29.46 Min. 2.28 1.93 0.18 0.11 35.64
CQFP 256 Nom. 2.67 2.29 0.20 0.15 36.00 31.5 BSC 0.50 BSC 7.75 70.00 BSC 65.90 BSC 75.00 75.40 8.45 Max. 3.06 2.65 0.22 0.18 36.36
Note: 1. All dimensions are in inches except CQ208 and CQ256, which are in millimeters. 2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
97
Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners.
http://www.actel.com
Actel Europe Ltd. Daneshill House, Lutyens Close Basingstoke, Hampshire RG24 8AG United Kingdom Tel: +44-(0)125-630-5600 Fax: +44-(0)125-635-5420 Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81-(0)3-3445-7671 Fax: +81-(0)3-3445-7668
5192641-2/1.00

▲Up To Search▲

Price & Availability of A1020A-1PG256B

	To Download A1020A-1PG256B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .